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QuoteRef: rymaJW3_1982
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references p-r
Topic:
code optimization by instruction reordering or scheduling
Topic:
code optimization
Reference
Rymarczyk, J.W., "Coding guidelines for pipelined processors", SIGPLAN, 17, 4, pp. 12-19 , March 1982 . Google
Other Reference
SIGARCH 10.2
13 ;;Quote: an address generation interlock occurs when a register is needed for address calculation but it hasn't been set yet
15 ;;Quote: an operand fetch interlock occurs when a memory location is needed but it is still being updated
16 ;;Quote: branches reduce the ability of a processor to prefetch instructions; especially when taken
18 ;;Quote: to prevent memory bank thrashing, array processing programs should use sequential access to storage
18 ;;Quote: sometimes pipeline gaps can be used for anticipatory prefetching into fast buffer registers
ThesaHelp: references p-r (245 items)
Topic: code optimization by instruction reordering or scheduling (16 items)
Topic: code optimization (54 items)