Quote: description of wide microinstruction for CM-1 Connection Machine; truth table on 2 bits and 16 flags, N/E/S/W pins for I/O

Note

Each nanoinstruction to a CM-1 processor cell is a horizontal microinstruction with the following components: A and B addresses of two bits to read from the 4K memory, which of 16 flags to read and which to write, which flag to check in which state to enable instruction execution (conditionalization), which of 256 possible truth tables of 3 inputs to write to the A address and which to write to the flags, and if used, which North/East/West/South pin to write to. ... [p. 77] [The eight special purpose flags in CM-1 are: NEWS input from North, East, West, or South neighbor, Cube input from routing neighbor for diagnostics, Router input/output of message address followed by data, Router transmission acknowledgement, daisychain input for linking 16 processor cells together, long parity of processor's 4K memory which provides error correction in conjunction with short parity bits, input pin, and the always zero flag.

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Topic: computer architecture (44 items)