67 ;;Quote: survey of consistency models for hardware-based shared memory systems; includes programmer-centric view of relaxed consistency models

69 ;;Quote: cache coherence by ordering writes to the same location does not satisfy sequential memory consistency since different locations may use different orderings

70 ;;Quote: write atomicity if writes to the same location are serialized and reads are disallowed until the write is visible to all processors

70 ;;Quote: compilers can violate sequential consistency by reordering shared memory operations or allocating shared memory to registers; like relaxed consistency, it is difficult to analyze

71 ;;Quote: relaxed memory consistency models differ in how they relax program order and write atomicity; e.g., a read may return another processor's write before it is globally visible

71 ;;Quote: relaxed memory consistency models often provide a fence instruction or other safety net to force synchronization; these allow compilers to safely optimize large regions of code

74 ;;Quote: programmers can identify synchronization and data operations in performance-critical areas for weak order optimization; example of programmer-centric approach to relaxed memory consistency