4 ;;Quote: hardware condition codes are difficult to implement because they are updated as side-effects; irregular structure

4 ;;Quote: instead of condition codes, MIPS uses a compare and branch instruction with 16 possible comparisons

4 ;;Quote: in a pipelined architecture, a branch is much more expensive than computation

5 ;;Quote: when condition codes are needed, MIPS has a Set Conditional instruction that sets a register to 0 or 1

6 ;;Quote: instead of querying devices, MIPS includes a 'surprise code' with each interrupt; pipe stage, type, and device-specific information

8 ;;Quote: MIPS provides special instructions for accessing bytes in packed arrays

9 ;;Quote: with simple hardware, the compiler is complex but program execution is simple and efficient

9 ;;Quote: the MIPS compiler reorganizes codes or inserts no-ops to avoid pipeline interlocks; uses follow sets

9 ;;Quote: MIPS uses delay slots for all branches

10 ;;Quote: instead of a stack machine, use load/store architectures without condition codes